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Standard Products
UT54LVDS217 Serializer
Data Sheet May 8, 2007
FEATURES 15 to 75 MHz shift clock support Low power consumption Power-down mode <216W (max) Cold sparing all pins Narrow bus reduces cable size and cost Up to 1.575 Gbps throughput Up to 197 Megabytes/sec bandwidth 325 mV (typ) swing LVDS devices for low EMI PLL requires no external components Rising edge strobe Radiation-hardened design; total dose irradiation testing to MIL-STD-883 Method 1019 - Total-dose: 300 krad(Si) and 1 Mrad(Si) - Latchup immune (LET > 100 MeV-cm2/mg) Packaging options: - 48-lead flatpack Standard Microcircuit Drawing 5962-01534 - QML Q and V compliant part
INTRODUCTION The UT54LVDS217 Serializer converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 75MHz, 21 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel. Using a 75MHz clock, the data throughput is 1.575 Gbit/s (197 Mbytes/sec). The UT54LVDS217 Serializer allows the use of wide, high speed TTL interfaces while reducing overall EMI and cable size. All pins have Cold Spare buffers. These buffers will be high impedance when VDD is tied to VSS.
21 CMOS/TTL INPUTS
TTL PARALLEL-TO-LVDS TTL PARALLEL -TO-LVDS
DATA (LVDS)
TRANSMIT CLOCK IN POWER DOWN
PLL
CLOCK (LVDS)
Figure 1. UT54LVDS217 Serializer Block Diagram
1
TxIN4 VDD TxIN5 TxIN6 GND TxIN7 TxIN8 VDD TxIN9 TxIN10 GND TxIN11 TxIN12 VDD TxIN13 TxIN14 GND TxIN15 TxIN16 TxIN17 VDD TxIN18 TxIN19 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UT54LVDS217
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
TxIN3 TxIN2 GND TxIN1 TxIN0 N/C LVDS GND TxOUT0TxOUT0+ TxOUT1TxOUT1+ LVDS VDD LVDS GND TxOUT2TxOUT2+ TxCLK OUTTxCLK OUT+ LVDS GND PLL GND PLL VDD PLL GND PWR DWN TxCLK IN TxIN20
PIN DESCRIPTION Pin Name
TxIN TxOUT+ TxOUTTxCLK IN TxCLK OUT+ TxCLK OUTPWR DWN
I/O
I O O I O O I
No.
21 3 3 1 1 1 1
Description
TTL level input Positive LVDS differential data output Negative LVDS differential data output TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN Positive LVDS differential clock output Negative LVDS differential clock output TTL level input. Assertion (low input) TRISTATEs the clock and data outputs, ensuring low current at power down. Power supply pins for TTL inputs and logic Ground pins for TTL inputs and logic Power supply pins for PLL Ground pins for PPL Power supply pin for LVDS output Ground pins for LVDS outputs
VDD GND PLL VDD PLL GND LVDS VDD LVDS GND
I I I I I I
4 5 1 2 1 3
Figure 2. UT54LVDS217 Pinout UT54LVDS217 TxIN
0 1 2
LVDS CABLE
MEDIA DEPENDENT DATA (LVDS)
UT54LVDS218 RxOUT
0 1 2
CMOS/ TTL
18 19 20
18 19 20
CLOCK (LVDS)
TxCLK GND PCB SHIELD Figure 3. UT54LVDS217 Typical Application PCB
RxCLK
ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS) SYMBOL VDD VI/O TSTG PD TJ JC II PARAMETER DC supply voltage Voltage on any pin4 Storage temperature Maximum power dissipation Maximum junction temperature2 Thermal resistance, junction-to-case3 DC input current LIMITS -0.3 to 4.0V -0.3 to (VDD + 0.3V) -65 to +150C 2W +150C 10C/W
10mA
Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175C during burn-in and lifetest. 3. Test per MIL-STD-883, Method 1012. 4. For cold spare mode (VDD = VSS), VI/O may be 0.3V to the maximum recommended operating VDD + 0.3V.
RECOMMENDED OPERATING CONDITIONS SYMBOL VDD, PLLVDD, LVDS VDD TC VIN PARAMETER Positive supply voltage Case temperature range DC input voltage LIMITS 3.0 to 3.6V -55 to +125C 0V to VDD
3
DC ELECTRICAL CHARACTERISTICS1 SYMBOL PARAMETER
(VDD = 3.3V-0.3V; -55C < TC < +125C) CONDITION MIN MAX UNIT
CMOS/TTL DC SPECIFICATIONS VIH VIL IIH IIL VCL ICS High-level input voltage Low-level input voltage High-level input current Low-level input current Input clamp voltage Cold Spare Leakage current VIN = 3.6V; VDD = 3.6V VIN = 0V; VDD = 3.6V ICL = -18mA VIN = 3.6V; VDD = VSS -20 2.0 GND -10 -10 VDD 0.8 +10 +10 -1.5 +20 V V A A V A
LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-) VOD5 VOD5 VOS5 VOS5 IOZ4 ICSOUT IOS2,3 Differential Output Voltage Change in VOD between complimentary output states Offset Voltage RL = 100 (See Figure 14) RL = 100 (See Figure 14)
-------------------------- RL = 100, Vos = Voh + Vol 2
250
400 35
mV mV V
1.120
1.410
Change in VOS between complimentary output states Output Three-State Current
RL = 100 PWR DWN = 0V VOUT = 0V or VDD VIN=3.6V, VDD = VSS VOUT+ or VOUT- = 0V -10
35 +10
mV mA
Cold Spare Leakage Current Output Short Circuit Current
-20
+20 5mA
Supply Current ICCL4 ICCZ4,6 Transmitter supply current with loads Power down current RL = 100 all channels (figure 5) CL = 5pF, f = 50MHz DIN = VSS PWR DWN = 0V, f = 0Hz 65.0 mA
60.0
A
Notes: 1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground. 2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, for a maximum duration of one second. 3. Guaranteed by characterization. 4. Devices are tested @ 3.6V only. 5. Clock outputs guaranteed by design. 6. Post 100Krad and 300Krad, ICCZ = 200A.
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AC SWITCHING CHARACTERISTICS1 (VDD = 3.0V to 3.6V; TA = -55C to +125C) SYMBOL LLHT2 LHLT2 TPPos02 TPPos12 TPPos22 TPPos32 TPPos42 TPPos52 TPPos62 TCCS3 TCIP TCIH4 TCIL4 TSTC2 THTC2 TCCD TPLLS TPDD PARAMETER LVDS Low-to-High Transition Time (Figure 5) LVDS High-to-Low Transition Time (Figure 5) Transmitter Output Pulse Position for Bit 0 (Figure 13) Transmitter Output Pulse Position for Bit 1(Figure 13) Transmitter Output Pulse Position for Bit 2 (Figure 13) Transmitter Output Pulse Position for Bit 3 (Figure 13) Transmitter Output Pulse Position for Bit 4 (Figure 13) Transmitter Output Pulse Position for Bit 5 (Figure 13) Transmitter Output Pulse Position for Bit 6 (Figure 13) Channel to Channel skew (Figure 7) TxCLK IN Period (Figure 8) TxCLK IN High Time (Figure 8) TxCLK IN Low Time (Figure 8) TxIN Setup to TxCLK IN (Figure 8) TxIN Hold to TxCLK IN (Figure 8) TxCLK IN to TxCLK OUT Delay (Figure 9) Transmitter Phase Lock Loop Set (Figure 10) Transmitter Powerdown Delay (Figure 12) 15MHz 75MHz 15MHz 75MHz 13.3 0.35Tcip 0.35Tcip 1.0 0.5 0.7 0.5 0.5 2.5 10 100 f=75MHz f=75MHz f=75MHz f=75MHz f=75MHz f=75MHz f=75MHz -0.18 1.72 3.63 5.53 7.44 9.34 11.25 MIN MAX 1.5 1.5 0.270 2.17 4.08 5.98 7.89 9.79 11.70 0.45 66.7 0.65Tcip 0.65Tcip UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns
Notes: 1. Recommend transistion time for TXCLK In is 1.0 to 6.0 ns (figure 6). 2. Guaranteed by characterization. 3. Channel to channel skew is defined as the difference between TPPOS max limit and TPPOS minimum limit. 4. Guaranteed by design.
T TxCLK IN
TxIN
Figure 4. Test Pattern
AC TIMING DIAGRAMS
Vdiff=(TxOUT+) - (TxOUT-) 80% 20% Vdiff 100 LLHT 80% 20% LHLT
TxOUT+ 5pF TxOUT-
Figure 5. UT54LVDS217 Output Load and Transition Times
90%
90% 10% TCIT TCIT
10% TXCLK IN
Figure 6. UT54LVDS217 Input Clock Transition Time
TCCS TxOUT0
TxOUT1
Vdiff= 0V
TxOUT2
TxCLK OUT TIME Notes: 1. Measurements at VDIFF = 0V 2. TCCS measured between earliest and latest LVDS edges. 3. TxCLK Differential Low-High Edge.
Figure 7. UT54LVDS217 Channel-to-Channel Skew
TCIP
Sample on L-H Edge
VDD/2 TxCLK IN
VDD/2 TCIH TCIL
VDD/2
TSTC TxIN 0-20 VDD/2 SETUP
THTC HOLD VDD/2
Figure 8. UT54LVDS217 Setup/Hold and High/Low Times
TxCLK IN
VDD/2 TCCD
TxCLK OUT
Vdiff= 0V
Figure 9. UT54LVDS217 Clock-to-Clock Out Delay
VDD VDD/2 POWER DOWN VDD VDD/2 VDD TPLLS
TxCLK IN
TxCLK OUT /
RxCLK IN
Vdiff = OV
Figure 10. UT54LVDS217 Phase Lock Loop Set Time
TxCLK OUT /
RxCLK IN
Previous Cycle TxOUT2 /
RxIN2
TxIN15-1 TxIN14-1 TxIN20 TxIN19 TxIN18
Next Cycle
TxIN17 TxIN16 TxIN15 TxIN14
TxOUT1 /
RxIN1
TxIN8-1
TxIN7-1
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
TxOUT0 /
RxIN0
TxIN1-1
TxIN0-1
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
Figure 11. UT54LVDS217 Parallel TTL Data Inputs Mapped to LVDS Outputs
POWER DOWN
VDD/2
TxCLK IN TPDD TxOUT THREE-STATE
Figure 12. Transmitter Powerdown Delay
TCLK TxCLK OUT /
Differential
Previous Cycle TxOUT2 /
(Single ended)
TxIN15-1 TxIN14-1 TxIN20 TxIN19 TxIN18
Next Cycle
TxIN17 TxIN16 TxIN15 TxIN14
TxOUT1 /
Single ended
TxIN8-1
TxIN7-1
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
TxOUT0 /
Single ended
TxIN1-1
TxIN0-1
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 Figure 13. LVDS Output Pulse Position Measurement
DOUT+ 20pF DIN Generator 50 D RL = 100 VOD
Driver Enabled
20pF
DOUT-
Figure 14. Driver VOD and VOS Test Circuit or Equivalent Circuit
PACKAGING
5
6
4
6
1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance with MIL-PRF-38535. 4. Lead position and colanarity are not measured. 5. ID mark symbol is vendor option. 6. With solder, increase maximum by 0.003.
Figure 15. 48-Lead Flatpack
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ORDERING INFORMATION UT54LVDS217 Serializer:
UT 54LVDS217 - * *
***
Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder)
Screening: (C) = Military Temperature Range flow (P) = Prototype flow
Package Type: (U) = 48-lead Flatpack (dual-in-line)
Access Time: Not applicable Device Type: UT54LVDS217 Serializer
Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. Military Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55C, room temp, and 125C. Radiation neither tested nor guaranteed.
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UT54LVDS217 Serializer: SMD
5962 - 01534
** * * *
Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (X) = 48 lead Flatpack (dual-in-line) Class Designator: (Q) = QML Class Q (V) = QML Class V
Device Type 01 = 50MHz LVDS Serializer (contacat factory) 02 = 75MHz LVDS Serializer Drawing Number: 01534 Total Dose (R) = 1E5 rad(Si) (F) = 3E5 rad(Si) (G) = 5E5 rad(Si) (H) = 1E6 rad(Si) Federal Stock Class Designator: No Options Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
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Aeroflex UTMC Microelectronic Systems Inc. (Aeroflex) reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties.
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